Hypergraph-Based Interconnection Networks for Large Multicomputers

Ould-Khaoua, Mohamed (1994) Hypergraph-Based Interconnection Networks for Large Multicomputers. PhD thesis, University of Glasgow.

Abstract

This thesis deals with issues pertaining to multicomputer interconnection networks namely topology, technology, switching method, and routing algorithm. It argues that a new class of regular low-dimensional hypergraph networks, the distributed crossbar switch hypermesh (DCSH), represents a promising alternative high-performance interconnection network for future large multicomputers to graph networks such as meshes, tori, and binary n-cubes, which have been widely used in current multicomputers. Channels in existing hypergraph and graph structures suffer from bandwidth limitations imposed by implementation technology. The first part of the thesis shows how the low-dimensional DCSH can use an innovative implementation scheme to alleviate this problem. It relies on the separation of processing and communication functions by physical layering in order to accommodate high wiring density and necessary message buffering, improving performance considerably. Various mathematical models of the DCSH, validated through discrete-event simulation, are then introduced. Effects of different switching methods (e.g., wormhole routing, virtual cut-through, and message switching), routing algorithms (e.g., restricted and random), and different switching element designs are investigated. Further, the impact on performance of different communication patterns, such as those including locality and hot-spots, are assessed. The remainder of the thesis compares the DCSH to other common hypergraph and graph networks assuming different implementation technologies, such as VLSI, multiple-chip technology, and the new layered implementation scheme. More realistic assumptions are introduced such as pipeline-bit transmission and non-zero delays through switching elements. The results show that the proposed structure has superior characteristics assuming equal implementation cost in both VLSI and multiple-chip technology. Furthermore, optimal performance is offered by the new layered implementation.

• Item Type: Thesis (PhD)
• Qualification Level: Doctoral
• Additional Information: Adviser: L M MacKenzie
• Keywords: Computer engineering
• Date of Award: 1994
• Depositing User: Enlighten Team
• Unique ID: glathesis:1994-76291
• Copyright: Copyright of this thesis is held by the author.
• Date Deposited: 19 Nov 2019 16:09
• Last Modified: 19 Nov 2019 16:09
• URI: https://theses.gla.ac.uk/id/eprint/76291