McKechnie, Paul Edward
Validation and verification of the interconnection of hardware intellectual property blocks for FPGA-based packet processing systems.
EngD thesis, University of Glasgow.
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As networks become more versatile, the computational requirement for supporting additional
functionality increases. The increasing demands of these networks can be met by Field Programmable
Gate Arrays (FPGA), which are an increasingly popular technology for implementing packet processing
systems. The fine-grained parallelism and density of these devices can be exploited to meet the
computational requirements and implement complex systems on a single chip. However, the increasing
complexity of FPGA-based systems makes them susceptible to errors and difficult to test and debug.
To tackle the complexity of modern designs, system-level languages have been developed to provide
abstractions suited to the domain of the target system. Unfortunately, the lack of formality in
these languages can give rise to errors that are not caught until late in the design cycle. This
thesis presents three techniques for verifying and validating FPGA-based packet processing systems
described in a system-level description language. First, a type system is applied to the system
description language to detect errors before implementation. Second, system-level transaction
monitoring is used to observe high-level events on-chip following implementation. Third, the
high-level information embodied in the system description language is exploited to allow the system
to be automatically instrumented for on-chip monitoring.
This thesis demonstrates that these techniques catch errors which are undetected by traditional
verification and validation tools. The locations of faults are specified and errors are caught
earlier in the design flow, which saves time by reducing synthesis iterations.
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