GALS NoC

Salisbury, Sean James (2015) GALS NoC. EngD thesis, University of Glasgow.

Due to Embargo and/or Third Party Copyright restrictions, this thesis is not available in this service.

Abstract

This portfolio thesis documents the work undertaken by the author for the Engineering Doctorate (EngD) programme. The research work completed for this thesis was undertaken at two sponsoring companies, Silistix and ARM.
Demand for more complex yet power efficient devices has led to demand for System-on-Chip integrated circuit designs. To achieve this, ever increasing numbers of functional units in the form of Intellectual Property are being integrated into System-on-Chip designs. To cope with the increased design complexity challenge two key technologies are starting to be adopted. These are Globally Asynchronous Locally Synchronous to provide the ability to compose systems and Network-on-Chip to provide on-chip connectivity. This portfolio thesis considers some of the remaining difficulties in constructing Network-on-Chips in Globally Asynchronous Locally Synchronous designs.
There are a number of major contributions presented in this thesis: the implementation of eleven orthogonal hazard defence circuit designs and techniques for Quasi-Delay Insensitive communication links; and the creation of a new Design-for-Test implementation and methodology enabling Quasi-Delay Insensitive Network-on-Chip components to achieve stuck-at test requirements in a commercial System-on-Chip design flow. Also presented is the creation of a test vehicle to enable analysis of synchronisation and serialisation within on-chip interconnects. The final contribution presented is a correctness and performance analysis of propagating memory barriers through on-chip interconnects to ensure correct system memory ordering and observation requirements.

Item Type: Thesis (EngD)
Qualification Level: Doctoral
Keywords: GALS, Globally asynchronous locally synchronous, seu, single event upset, dft, design for test, asynchronous, synchronization, qdi, memory barrier
Subjects: Q Science > QA Mathematics > QA75 Electronic computers. Computer science
T Technology > TK Electrical engineering. Electronics Nuclear engineering
Colleges/Schools: College of Science and Engineering > School of Engineering
Funder's Name: UNSPECIFIED
Supervisor's Name: Efthymiou, Dr. Aristides
Date of Award: 2015
Embargo Date: 2 May 2018
Depositing User: mr sean j Salisbury
Unique ID: glathesis:2015-6316
Copyright: Copyright of this thesis is held by the author.
Date Deposited: 04 May 2015 08:31
Last Modified: 04 May 2015 08:59
URI: http://theses.gla.ac.uk/id/eprint/6316

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