The development of planar high-K/III-V p-channel MOSFETs for post-silicon CMOS

Peralagu, Uthayasankaran (2016) The development of planar high-K/III-V p-channel MOSFETs for post-silicon CMOS. PhD thesis, University of Glasgow.

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Abstract

Conventional Si complementary-metal-oxide-semiconductor (CMOS) scaling is fast approaching its limits. The extension of the logic device roadmap for future enhancements in transistor performance requires non-Si materials and new device architectures. III-V materials, due to their superior electron transport properties, are well poised to replace Si as the channel material beyond the 10nm technology node to mitigate the performance loss of Si transistors from further reductions in supply voltage to minimise power dissipation in logic circuits. However several key challenges, including a high quality dielectric/III-V gate stack, a low-resistance source/drain (S/D) technology, heterointegration onto a Si platform and a viable III-V p-metal-oxide-semiconductor field-effect-transistor (MOSFET), need to be addressed before III-Vs can be employed in CMOS.

This Thesis specifically addressed the development and demonstration of planar III-V p-MOSFETs, to complement the n-MOSFET, thereby enabling an all III-V CMOS technology to be realised. This work explored the application of InGaAs and InGaSb material systems as the channel, in conjunction with Al2O3/metal gate stacks, for p-MOSFET development based on the buried-channel flatband device architecture. The body of work undertaken comprised material development, process module development and integration into a robust fabrication flow for the demonstration of p-channel devices.

The parameter space in the design of the device layer structure, based around
the III-V channel/barrier material options of In<sub>x≥0.53</sub>Ga<sub>1-x</sub>As/In<sub>0.52</sub>Al<sub>0.48</sub>As and In<sub>x≥0.1</sub>Ga<sub>1-x</sub>Sb/AlSb, was systematically examined to improve hole channel transport. A mobility of 433 cm<sup>2</sup>/Vs, the highest room temperature hole mobility of any InGaAs quantum-well channel reported to date, was obtained for the In<sub>0.85</sub>Ga<sub>0.15</sub>As (2.1% strain) structure.

S/D ohmic contacts were developed based on thermally annealed Au/Zn/Au metallisation and validated using transmission line model test structures. The effects of metallisation thickness, diffusion barriers and de-oxidation conditions were examined. Contacts to InGaSb-channel structures were found to be sensitive to de-oxidation conditions.

A fabrication process, based on a lithographically-aligned double ohmic patterning approach, was realised for deep submicron gate-to-source/drain gap (L<sub>side</sub>) scaling to minimise the access resistance, thereby mitigating the effects of parasitic S/D series resistance on transistor performance. The developed process yielded gaps as small as 20nm.

For high-k integration on GaSb, ex-situ ammonium sulphide ((NH<sub>4</sub>)<sub>2</sub>S) treatments, in the range 1%-22%, for 10min at 295K were systematically explored for improving the electrical properties of the Al<sub>2</sub>O<sub>3</sub>/GaSb interface. Electrical and physical characterisation indicated the 1% treatment to be most effective with interface trap densities in the range of 4 - 10×10<sup>12</sup>cm<sup>-2</sup>eV<sup>-1</sup> in the lower half of the bandgap. An extended study, comprising additional immersion times at each sulphide concentration, was further undertaken to determine the surface roughness and the etching nature of the treatments on GaSb.

A number of p-MOSFETs based on III-V-channels with the most promising hole transport and integration of the developed process modules were successfully demonstrated in this work. Although the non-inverted InGaAs-channel devices showed good current modulation and switch-off characteristics, several aspects of performance were non-ideal; depletion-mode operation, modest drive current (I<sub>d,sat</sub>=1.14mA/mm), double peaked transconductance (g<sub>m</sub>=1.06mS/mm), high subthreshold swing (SS=301mV/dec) and high on-resistance (R<sub>on</sub>=845kΩ.μm). Despite demonstrating substantial improvement in the on-state metrics of I<sub>d,sat</sub> (11×), g<sub>m</sub> (5.5×) and R<sub>on</sub> (5.6×), inverted devices did not switch-off. Scaling gate-to-source/drain gap (L<sub>side</sub>) from 1μm down to 70nm improved I<sub>d,sat</sub> (72.4mA/mm) by a factor of 3.6 and gm (25.8mS/mm) by a factor of 4.1 in inverted InGaAs-channel devices. Well-controlled current modulation and good saturation behaviour was observed for InGaSb-channel devices. In the on-state In<sub>0.3</sub>Ga<sub>0.7</sub>Sb-channel (I<sub>d,sat</sub>=49.4mA/mm, g<sub>m</sub>=12.3mS/mm, R<sub>on</sub>=31.7kΩ.μm) and In<sub>0.4</sub>Ga<sub>0.6</sub>Sb-channel (I<sub>d,sat</sub>=38mA/mm, g<sub>m</sub>=11.9mS/mm, R<sub>on</sub>=73.5kΩ.μm) devices outperformed the InGaAs-channel devices. However the devices could not be switched off. These findings indicate that III-V p-MOSFETs based on InGaSb as opposed to InGaAs channels are more suited as the p-channel option for post-Si CMOS.

Item Type: Thesis (PhD)
Qualification Level: Doctoral
Keywords: CMOS, p-MOSFET, III-V, InGaAs, In(Ga)Sb, gate stack, high-k dielectric, hole mobility, process integration, surface passivation, electron beam lithography.
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Colleges/Schools: College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Funder's Name: Semiconductor Research Corporation (SRC), USA
Supervisor's Name: Thayne, Professor Iain G.
Date of Award: 2016
Depositing User: Mr Uthayasankaran Peralagu
Unique ID: glathesis:2016-7568
Copyright: Copyright of this thesis is held by the author.
Date Deposited: 09 Sep 2016 08:16
Last Modified: 24 Oct 2016 09:51
URI: http://theses.gla.ac.uk/id/eprint/7568

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