The development of sub-25 nm III-V High Electron Mobility Transistors

Bentley, Steven (2009) The development of sub-25 nm III-V High Electron Mobility Transistors. PhD thesis, University of Glasgow.

Full text available as:
[thumbnail of 2009bentleyphd.pdf] PDF
Download (12MB)
Printed Thesis Information:


High Electron Mobility Transistors (HEMTs) are crucially important devices in microwave circuit applications. As the technology has matured, new applications have arisen, particularly at millimetre-wave and sub-millimetre wave frequencies. There now exists great demand for low-visibility, security and medical imaging in addition to telecommunications applications operating at frequencies well above 100 GHz.

These new applications have driven demand for high frequency, low noise device operation; key areas in which HEMTs excel. As a consequence, there is growing incentive to explore the ultimate performance available from such devices. As with all FETs, the key to HEMT performance optimisation is the reduction of gate length, whilst optimally scaling the rest of the device and minimising parasitic extrinsic influences on device performance.

Although HEMTs have been under development for many years, key performance metrics have latterly slowed in their evolution, largely due to the difficulty of fabricating devices at increasingly nanometric gate lengths and maintaining satisfactory scaling and device performance. At Glasgow, the world-leading 50 nm HEMT process developed in 2003 had not since been improved in the intervening five years.

This work describes the fabrication of sub-25 nm HEMTs in a robust and repeatable manner by the use of advanced processing techniques: in particular, electron beam lithography and reactive ion etching. This thesis describes firstly the development of robust gate lithography for sub-25 nm patterning, and its incorporation into a complete device process flow. Secondly, processes and techniques for the optimisation of the complete device are described.

This work has led to the successful fabrication of functional 22 nm HEMTs and the development of 10 nm scale gate pattern transfer: simultaneously some of the shortest gate length devices reported and amongst the smallest scale structures ever lithographically defined on III-V substrates. The first successful fabrication of implant-isolated planar high-indium HEMTs is also reported amongst other novel secondary processes.

Item Type: Thesis (PhD)
Qualification Level: Doctoral
Keywords: HEMT, III-V, FET, electron beam lithography, reactive ion etching, T-gate, nanoelectronics
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Colleges/Schools: College of Science and Engineering > School of Engineering
Supervisor's Name: Thayne, Prof. Iain
Date of Award: 2009
Depositing User: Mr Steven Bentley
Unique ID: glathesis:2009-1301
Copyright: Copyright of this thesis is held by the author.
Date Deposited: 12 Nov 2009
Last Modified: 10 Dec 2012 13:37

Actions (login required)

View Item View Item


Downloads per month over past year