Accurate statistical circuit simulation in the presence of statistical variability

Asenov, Plamen (2013) Accurate statistical circuit simulation in the presence of statistical variability. PhD thesis, University of Glasgow.

Abstract

Semiconductor device performance variation due to the granular nature of charge and matter has become a key problem in the semiconductor industry. The main sources of this ‘statistical’ variability include random discrete dopants (RDD), line edge roughness (LER) and metal gate granularity (MGG). These variability sources have been studied extensively, however a methodology has not been developed to accurately represent this variability at a circuit and system level. In order to accurately represent statistical variability in real devices
the GSS simulation toolchain was utilised to simulate 10,000 20/22nm n- and
p-channel transistors including RDD, LER and MGG variability sources. A
statistical compact modelling methodology was developed which accurately
captured the behaviour of the simulated transistors, and produced compact
model parameter distributions suitable for advanced compact model generation
strategies like PCA and NPM. The resultant compact model libraries
were then utilised to evaluate the impact of statistical variability on SRAM
design, and to quantitatively evaluate the difference between accurate compact
model generation using NPM with the Gaussian VT methodology. Over 5 million
dynamic write simulations were performed, and showed that at advanced
technology nodes, statistical variability cannot be accurately represented using
Gaussian VT . The results also show that accurate modelling techniques can
help reduced design margins by elimiating some of the pessimism of standard
variability modelling approaches.

• Item Type: Thesis (PhD)
• Qualification Level: Doctoral
• Keywords: Statistical Variability, MOSFET, compact models, SRAM, simulations
• Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
• Colleges/Schools: College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
• Supervisor's Name: Roy, Prof. S.
• Date of Award: 2013
• Depositing User: Mr P Asenov
• Unique ID: glathesis:2013-4996
• Copyright: Copyright of this thesis is held by the author.
• Date Deposited: 06 Mar 2014 08:28
• Last Modified: 06 Mar 2014 08:30
• URI: https://theses.gla.ac.uk/id/eprint/4996