Self-aligned short gate length III-V HEMT technology

Moran, David A.J. (2004) Self-aligned short gate length III-V HEMT technology. PhD thesis, University of Glasgow.

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This thesis presents a ne- approach to the fabrication of short gate length HI-V High Electron Mobility Transistors (HEMTs) that reduces the impact of external parasitic elements, and in particular access resistances, upon device performance. This was approached through the development of a self-aligned T-gate process with non-annealed ohmic contacts. The process was used to fabricate both GaAs pseudomorphic HEMT and subsequently lattice matched InP devices. In addition, a new selective recess etch was developed for cap layers containing indium. Characterisation of the self-aligned GaAs pHEMT devices indicated good RF performance with fT = 137GHz and fmax = 182GHz for devices of 120nm gate length, although DC performance was found to be restricted by the unoptimised non-annealed ohmic process. Analysis of the operation of the GaAs pHEMT devices led to the design and growth of an InP material structure incorporating double delta doping to minimise the non-annealed ohmic contact resistance. Using this optimised structure, standard and self-aligned HEMT devices with gates of length 120nm and 70nm were fabricated for comparison. The benefits and limitations of the self-aligned process were highlighted by comparing the performance of the self-aligned and standard devices. The self-aligned 120nm devices had fT = 220GHz and fmax = 255GHz, which rose to fT = 270GHz and fmax = 300GHz for the 70nm devices. Transconductance figures of up to 1500mS/mm were extracted for both. It is concluded that the self-aligned process, although beneficial to device performance at the 120nm, and to a lesser degree the 70nm node, would begin to degrade performance at reduced gate lengths due to increased parasitic gate capacitances. The non-annealed ohmic technology developed in this work provides a route that minimises parasitic resistances and increases performance without the increased parasitic gate capacitances associated with a self-aligned gate approach. A possible solution for the minimisation of parasitic gate capacitances using a self-aligned approach is proposed.

Item Type: Thesis (PhD)
Qualification Level: Doctoral
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Colleges/Schools: College of Science and Engineering > School of Engineering
Supervisor's Name: Thayne, Prof. lain
Date of Award: 2004
Depositing User: Miss Louise Annan
Unique ID: glathesis:2004-6577
Copyright: Copyright of this thesis is held by the author.
Date Deposited: 23 Jul 2015 11:01
Last Modified: 23 Jul 2015 11:01

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