Scaling and intrinsic parameter fluctuations in nanoCMOS devices

Adamu-Lema, Fikru (2005) Scaling and intrinsic parameter fluctuations in nanoCMOS devices. PhD thesis, University of Glasgow.

Abstract

The core of this thesis is a thorough investigation of the scaling properties of conventional nano-CMOS MOSFETs, their physical and operational limitations and intrinsic parameter fluctuations. To support this investigation a well calibrated 35 nm physical gate length real MOSFET fabricated by Toshiba was used as a reference transistor. Prior to the start of scaling to shorter channel lengths, the simulators were calibrated against the experimentally measured characteristics of the reference device. Comprehensive numerical simulators were then used for designing the next five generations of transistors that correspond to the technology nodes of the latest International Technology Roadmap for Semiconductors (lTRS). The scaling of field effect transistors is one of the most widely studied concepts in semiconductor technology. The emphases of such studies have varied over the years, being dictated by the dominant issues faced by the microelectronics industry. The research presented in this thesis is focused on the present state of the scaling of conventional MOSFETs and its projections during the next 15 years. The electrical properties of conventional MOSFETs; threshold voltage (VT), subthreshold slope (S) and on-off currents (lon, Ioffi ), which are scaled to channel lengths of 35, 25, 18, 13, and 9 nm have been investigated. In addition, the channel doping profile and the corresponding carrier mobility in each generation of transistors have also been studied and compared. The concern of limited solid solubility of dopants in silicon is also addressed along with the problem of high channel doping concentrations in scaled devices. The other important issue associated with the scaling of conventional MOSFETs are the intrinsic parameter fluctuations (IPF) due to discrete random dopants in the inversion layer and the effects of gate Line Edge Roughness (LER). The variations of the three important MOSFET parameters (loff, VT and Ion), induced by random discrete dopants and LER have been comprehensively studied in the thesis. Finally, one of the promising emerging CMOS transistor architectures, the Ultra Thin Body (UTB) SOl MOSFET, which is expected to replace the conventional MOSFET, has been investigated from the scaling point of view.

• Item Type: Thesis (PhD)
• Qualification Level: Postdoctoral
• Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
• Colleges/Schools: College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
• Supervisor's Name: Asenov, Professor Asen and Roy, Doctor Scott
• Date of Award: September 2005
• Embargo Date: September 2005
• Depositing User: Mrs Marie Cairney
• Unique ID: glathesis:2005-7086
• Copyright: Copyright of this thesis is held by the author.
• Date Deposited: 11 Feb 2016 12:21
• Last Modified: 09 Aug 2019 15:49
• URI: https://theses.gla.ac.uk/id/eprint/7086