Architectures and optimisations for FPGA-based simulation of quantum circuits

Moawad, Youssef (2025) Architectures and optimisations for FPGA-based simulation of quantum circuits. PhD thesis, University of Glasgow.

Abstract

The increasing complexity and scale of quantum algorithms, coupled with the current limitations of physical quantum hardware, have led to a growing need for efficient quantum circuit simulation techniques. While CPUs and GPUs have traditionally been used for simulating quantum circuits, their energy consumption and scalability issues have prompted exploration into alternative platforms. Field-Programmable Gate Arrays present a promising alternative, offering the potential for customisable parallelism, energy efficiency, and flexible hardware configurations. This thesis investigates the use of FPGA architectures for Full State Vector Quantum Circuit Simulation, evaluating their performance, scalability, and energy efficiency relative to traditional CPU and GPU platforms.

The core aim of this work is to explore whether scalable FPGA architectures can be designed for quantum circuit simulation, and to assess their comparative performance and energy efficiency against established CPU and GPU solutions. The work was guided by several research questions: Can FPGA architectures be optimised for quantum circuit simulation? How does the performance of FPGA architectures scale with hardware utilisation? What types of circuits benefit most from FPGA-based simulation? Is there a performance-per-Watt advantage to using FPGAs over GPUs and CPUs?

To answer these questions, a variety of FPGA-based architectures were designed and evaluated. The architectural approaches investigated include Direct Iteration Processing, Buffered Architectures, and Gate Fusion Architectures. Each of these architectures was tested on benchmark quantum circuits, including Quantum Fourier Transform, and Grover’s search algorithm, representing a range of qubit counts and gate complexities. These architectures were compared in terms of scalability, execution time, and energy consumption, with their performance assessed against CPU and GPU implementations. One of the key contributions of this thesis is a controlled gate scheduling optimisation designed to improve performance for control-heavy circuits (i.e. circuits with a high number of controlled and multi-controlled gates). This architecture demonstrated substantial performance improvements for some circuits, where it was up to 5× faster than the baseline architecture. While the GPU still outperformed the FPGA in raw speed, the optimised architecture showed a significant energy advantage, consuming 2.6× less energy than the GPU for circuits with a high density of controlled gates. This highlights the potential of FPGA architectures to outperform traditional platforms in energy-constrained environments.

This work also presents a set of circuit width reduction techniques aimed at improving the scalability and efficiency of quantum circuit simulations on FPGA hardware. These techniques reduce the number of qubits required by identifying and transforming portions of the circuit that can be simplified without affecting the overall computation. Initially developed for circuits defining algorithms employing computational basis data encoding, the techniques were extended to handle circuits implementing algorithms employing the more widely-used amplitude-based data encoding approach, demonstrating their versatility. These optimisations were applied to circuits for computational fluid dynamics and quantum arithmetic, leading to more efficient use of FPGA memory and computational resources.

The introduced FPGA-based quantum circuit simulation platform is, to our knowledge, the first of its kind capable of simulating general-purpose quantum circuits, rather than being limited to specific algorithms or gate sets. Unlike many existing FPGA simulators that are specialised for particular quantum algorithms, such as Grover’s search or the Quantum Fourier Transform, this platform is designed to simulate any quantum circuit regardless of its structure or gate complexity, at high numbers of qubits (> 25). We simulate general-purpose quantum circuits of up to 29 qubits in this work, but in theory, the platform can scale up to any number of qubits, given sufficient memory resources. This level of flexibility, combined with the ability to handle larger quantum systems, positions this platform as a significant step forward in FPGA-based quantum circuit simulation, making it a versatile and scalable tool for both research and practical quantum computing applications.

Overall, this thesis demonstrates that while FPGAs may not match the raw execution speed of GPUs, they offer significant advantages in terms of energy efficiency for quantum circuit simulation, particularly for control-heavy circuits. The control scheduling optimisation and buffering strategies were found to significantly improve performance, especially for circuits with high controlled-gate density. However, challenges remain in terms of scalability, with High-Level Synthesis limitations posing barriers to further performance gains. The use of multi-FPGA clusters and further advancements in High-Level Synthesis tools could address these limitations and enable FPGAs to handle larger quantum circuits more efficiently.

• Item Type: Thesis (PhD)
• Qualification Level: Doctoral
• Subjects: Q Science > QA Mathematics > QA75 Electronic computers. Computer science
• Colleges/Schools: College of Science and Engineering > School of Computing Science
• Supervisor's Name: Vanderbauwhede, Professor Wim and Steijl, Dr. Rene
• Date of Award: 2025
• Depositing User: Theses Team
• Unique ID: glathesis:2025-84894
• Copyright: Copyright of this thesis is held by the author.
• Date Deposited: 14 Feb 2025 15:24
• Last Modified: 14 Feb 2025 15:27
• Thesis DOI: 10.5525/gla.thesis.84894
• URI: https://theses.gla.ac.uk/id/eprint/84894

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