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Statistical modelling of nano CMOS transistors with surface potential compact model PSP

Dideban, Daryoosh (2012) Statistical modelling of nano CMOS transistors with surface potential compact model PSP. PhD thesis, University of Glasgow.

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Abstract

The development of a statistical compact model strategy for nano-scale CMOS transistors is presented in this thesis. Statistical variability which arises from the discreteness of charge and granularity of matter plays an important role in scaling of nano CMOS transistors especially in sub 50nm technology nodes. In order to achieve reasonable performance and yield in contemporary CMOS designs, the statistical variability that affects the circuit/system performance and yield must be accurately represented by the industry standard compact models. As a starting point, predictive 3D simulation of an ensemble of 1000 microscopically different 35nm gate length transistors is carried out to characterize the impact of statistical variability on the device characteristics. PSP, an advanced surface potential compact model that is selected as the next generation industry standard compact model, is targeted in this study. There are two challenges in development of a statistical compact model strategy. The first challenge is related to the selection of a small subset of statistical compact model parameters from the large number of compact model parameters. We propose a strategy to select 7 parameters from PSP to capture the impact of statistical variability on current-voltage characteristics. These 7 parameters are used in statistical parameter extraction with an average RMS error of less than 2.5% crossing the whole operation region of the simulated transistors. Moreover, the accuracy of statistical compact model extraction strategy in reproducing the MOSFET electrical figures of merit is studied in detail. The results of the statistical compact model extraction are used for statistical circuit simulation of a CMOS inverter under different input-output conditions and different number of statistical parameters. The second challenge in the development of statistical compact model strategy is associated with statistical generation of parameters preserving the distribution and correlation of the directly extracted parameters. By using advanced statistical methods such as principal component analysis and nonlinear power method, the accuracy of parameter generation is evaluated and compared to directly extracted parameter sets. Finally, an extension of the PSP statistical compact model strategy to different channel width/length devices is presented. The statistical trends of parameters and figures of merit versus channel width/length are characterized.

Item Type: Thesis (PhD)
Qualification Level: Doctoral
Keywords: Nano CMOS, compact modelling, statistical variability, PSP
Subjects: T Technology > T Technology (General)
Colleges/Schools: College of Science and Engineering > School of Engineering
Supervisor's Name: Asenov, Prof. Asen
Date of Award: 2012
Depositing User: Dr Daryoosh Dideban
Unique ID: glathesis:2012-3257
Copyright: Copyright of this thesis is held by the author.
Date Deposited: 13 Mar 2012
Last Modified: 10 Dec 2012 14:05
URI: http://theses.gla.ac.uk/id/eprint/3257

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