Numerical simulation of sub-100 nm strained Si/SiGe MOSFETs for RF and CMOS applications

Yang, Lianfeng (2004) Numerical simulation of sub-100 nm strained Si/SiGe MOSFETs for RF and CMOS applications. PhD thesis, University of Glasgow.

Full text available as:
[img]
Preview
PDF
Download (20MB) | Preview

Abstract

Drift-Diffusion, Hydrodynamic and Monte Carlo simulations have been used in this work to simulate strained Si/SiGe devices for RF and CMOS applications. For numerical simulations of Si/SiGe devices, strain effects on the band structure of Si have been analyzed and analytical expressions are presented for parameters related to the bandgap and band alignment of Si/SiGe heterostructure. Optimization of n-type buried strained Si channel Si/SiGe MODFETs has been carried out in order to achieve high RF performance and high linearity. The impact of both lateral and vertical device geometries and different doping strategies has been investigated. The impact of the Ge content of the SiGe buffer on the performance of p-type surface channel strained Si/SiGe MOSFETs has been studied. Hydrodynamic device simulations have been used to assess the device performance of p-type strained Si/SiGe MOSFETs down to 35 nm gate lengths. Well-tempered strained Si MOSFETs with halo implants around the source/drain regions have been simulated and compared with those devices possessing only a single retrograde channel doping. The calibrations in respect of sub-100 nm Si and strained Si MOSFETs fabricated by IBM lead to a scaling study of those devices at 65 nm, 45 nm and 35 nm gate lengths. Using Drift-Diffusion simulations, ring oscillator circuit behaviour has been evaluated. Strained Si on insulator (SSOI) circuits have also been simulated and compared with strained Si circuits, Si circuits employing conventional surface channel MOSFETs along with SOI devices. Ensemble Monte Carlo simulations have been used to evaluate the device performance of n-type strained Si MOSFETs. A non-perturbative interface roughness scattering model has been used and validated by calibrating with respect to experimental mobility behaviour and device characteristics. The impact of interface roughness on the performance enhancement of strained Si MOSFETs has been investigated and evidence for reduced interface roughness scattering is presented, i.e., a smoother interface is suggested in strained Si MOSFETs. A 35 nm gate length Toshiba Si MOSFET has been simulated and the performance enhancement of 35 nm strained Si MOSFETs over the Toshiba Si device is predicted. Monte Carlo simulations are also employed to investigate the performance degradation due to soft-optical phonon scattering, which arises with the introduction of high-K gate dielectrics. Based on the device structures of the calibrated sub-100 nm n-type conventional and strained Si IBM MOSFETs, significant current degradation has been observed in devices with high-K gate dielectrics, HfO2 and Al2O3.

Item Type: Thesis (PhD)
Qualification Level: Doctoral
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Colleges/Schools: College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
Funder's Name: UNSPECIFIED
Supervisor's Name: Barker, Professor John R.
Date of Award: 2004
Depositing User: Ms Dawn Pike
Unique ID: glathesis:2004-5349
Copyright: Copyright of this thesis is held by the author.
Date Deposited: 04 Jul 2014 13:19
Last Modified: 04 Jul 2014 13:19
URI: http://theses.gla.ac.uk/id/eprint/5349

Actions (login required)

View Item View Item

Downloads

Downloads per month over past year