Calculation of potentials induced by stressors on semiconducting heterostructures

Petticrew, David (1999) Calculation of potentials induced by stressors on semiconducting heterostructures. MSc(R) thesis, University of Glasgow.

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Abstract

I have calculated the potential energy induced by stressors on the surface of a semiconducting heterostructure with 43m symmetry. The stressors may be single gates of arbitrary shape or one- and two-dimensional arrays of such gates, and I give results for an arbitrary surface. When the gates are metal, the strain arises from the differential thermal contraction of the gates and the substrate. Strain can also be induced by including a deliberately strained layer in the heterostructure and partly etching it away. The strain couples to the electrons by the deformation potential and the piezoelectric effect. The deformation potential does not depend on orientation but the piezoelectric effect usually dominates, and its angular dependence breaks the symmetry of the gate. I provide direct results in real space for single stripe gates, which is useful because even fast Fourier transforms take time and computing power. I also provide results in Fourier space for arrays of stripe gates, single circular and square gates and two- dimensional arrays of such gates. I consider the (100), (110), (111) and (311) surfaces in detail. Of these, the (111) surface may prove to be attractive for experiments since the piezoelectric effect is both strong and approximately isotropic. Harnessing this potential has allowed a range of new experiments on lateral surface superlattices to be designed and carried out at Glasgow. These have utilised the piezoelectric effect to produce a potential that has half the period of the fabricated structure. The strong potential induced by the piezoelectric effect has also revealed new features in the transport through a superlattice. These calculations have also shown that the piezoelectric potential can no longer be ignored when designing or modelling structures built on piezoelectric semiconductors, which include GaAs and other III-V materials. I have shown that placing a gate on the surface will produce a potential of around 1 meV at a depth roughly equal to half the width of the gate, which will have a measurable effect on devices. I also show how the piezoelectric potential can be minimised or eliminated if possible.

Item Type: Thesis (MSc(R))
Qualification Level: Masters
Additional Information: Adviser: John Davies
Keywords: Electrical engineering
Date of Award: 1999
Depositing User: Enlighten Team
Unique ID: glathesis:1999-71281
Copyright: Copyright of this thesis is held by the author.
Date Deposited: 10 May 2019 10:49
Last Modified: 10 May 2019 10:49
URI: http://theses.gla.ac.uk/id/eprint/71281

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