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Investigation into digital circuit design with GaAs/Ga2O3 heterostructure MOSFETs

Paluchowski Caldwell, Sonia Helena (2009) Investigation into digital circuit design with GaAs/Ga2O3 heterostructure MOSFETs. EngD thesis, Universities of Edinburgh, Glasgow, Heriot-Watt, and Strathclyde.

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Abstract

In this thesis, GaAs heterostructure MOSFETs are investigated as a potential technology for digital circuit design. The devices under investigation are 0.6 μm gate length, enhancement mode, heterostructure MOSFETs, with a high-κ dielectric (Ga2O3), and an InGaAs channel. Historically silicon CMOS technology has been the natural choice for digital circuits, however the realisation of GaAs MOSFET digital circuits could allow full integration of RF, optoelectronic and digital circuits on a single system-on-chip. Additionally, there are potential performance advantages in using GaAs due to it's high electron mobility. For the first time compact models of complimentary GaAs/Ga2O3 MOS are developed to enable an investigation into establishing a digital design methodology for GaAs MOS. Drift-diffusion models are developed and calibrated to measured device data. These models then provide information on the necessary device parameters to build compact models of these devices. BSIM3v3.2 compact models are developed based on this to enable GaAs MOS technology to be investigated using standard circuit design tools. The compact models have been adapted to ensure that they are physically relevant for GaAs devices. This includes some necessary approximations using effective medium theory. Further adjustments, or ratio corrections, are introduced to ensure that the internal physical parameters of BSIM will be correct. The models are compared to similarly-sized silicon devices to investigate the difference in performance between GaAs and silicon MOSFETs. As expected, the GaAs NMOS devices demonstrate improvements in drive current over silicon. However, the GaAs PMOS devices do not offer this advantage due to low hole mobility. Therefore, as a consequence of the high mobility ratio in GaAs, it is important to consider alternative digital design methodologies to CMOS to optimise performance. The performance of benchmark circuits is investigated for this technology in various digital design styles including CMOS, NMOS saturated enhancement load, and NMOS precharge. GaAs digital circuits gain a signifcant advantage in using alternative design styles to CMOS due to the relatively poor performance of the PMOS devices. In using the alternative styles the number of PMOS devices used can be minimised, and it is shown that NMOS precharge offers both speed and power advantages for this technology. The particular GaAs technology investigated does not outperform silicon in terms of speed and power. However, it has allowed a methodology to be established for future device generations, where performance is anticipated to improve signifcantly.

Item Type: Thesis (EngD)
Qualification Level: Doctoral
Keywords: GaAs MOS, digital logic, compact models, drift-diffusion modelling
Subjects: T Technology > T Technology (General)
Q Science > QA Mathematics
Colleges/Schools: College of Science and Engineering > School of Engineering
Supervisor's Name: Cumming, Prof. David R.S.
Date of Award: 2009
Depositing User: Mrs Sonia Helena Paluchowski Caldwell
Unique ID: glathesis:2009-861
Copyright: Copyright of this thesis is held by the author.
Date Deposited: 11 Jun 2009
Last Modified: 10 Dec 2012 13:27
URI: http://theses.gla.ac.uk/id/eprint/861

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