Realisation of III-V Tunnel-FET with in-situ ultimate scaled gate stack for high performance power efficient CMOS

Fu, Yen-Chun (2018) Realisation of III-V Tunnel-FET with in-situ ultimate scaled gate stack for high performance power efficient CMOS. PhD thesis, University of Glasgow.

Abstract

The main objective of this thesis is realising a non-planar III-V Tunnel-FET for low power device applications. The differentiating aspect of this work is based around clustered inductively coupled plasma (ICP) etch and atomic layer deposition (ALD) tools. This approach was intended to mitigate native oxide formation on etched III-V surfaces prior to gate stack deposition by ALD. The use of a cluster tool also offers the benefit of cleaning III-V surfaces “in-situ” using low damage plasma based approaches. In addition, activity on scaling the equivalent oxide thickness of the gate stack and evaluating different heterostructures are explored in this work for the realisation of high performance TunnelFET.

Initially, gate stacks on both p- and n- (110)-oriented In0.53Ga0.47As were examined to understand the basic electrical properties of these interfaces, important for non-planar device architectures. An optimised process, based on ex-situ sulphur-based passivation before ALD of gate dielectrics, and forming gas annealing (FGA) after gate metal deposition, is demonstrated for the first time to show significant Fermi level movement through the bandgap. Quantitatively, interface state density (Dit) values in the range of 0.87-1.8 × 1012 cm-2eV-1 around the midgap energy level were obtained. The lowest Dit value is estimated to be 3.1 × 1012 cm-2eV-1 close to the conduction band edge showing the combination of sulphur passivation and (FGA) is effective is passivating the trap states in the upper half of the bandgap on Al2O3/In0.53Ga0.47As (110) MOSCAPs. Furthermore, by analysis of CV hysteresis biasing at 1.1 V beyond the flatband voltage, the border trap density on n-type MOSCAPs was observed to reduce, after FGA from 1.8 × 1012 cm-2 to 5.3 × 1011 cm-2. The result observed in p-type MOSCAPs is in contrast, with increasing border trap density from 7.3 × 1011 cm-2 to 1.4 × 1012 cm-2 under the similar bias condition, i.e. the FGA process is not as effective in passivating states close to the valence band. In addition, the analysis undertaken in this thesis determined the value of the conduction band offset at the Al2O3/In0.53Ga0.47As (110) to be is 1.81eV – the first report of this parameter.

The non-planar devices of this work also require low damage etching processes for fin/wire formation. Therefore, the performance of in-situ deposited gate stacks to In0.53Ga0.47As (100)- and (110)-oriented substrates which had been subjected to a CH4/Cl2/H2 based ICP etch chemistry, which forms vertical InGaAs sidewall profiles, were assessed. Based on CV and IV, and X-ray Photo-Spectroscopy (XPS) spectral analyses, the performance of gate stacks deposited on (110)-oriented In0.53Ga0.47As subjected to a ICP dry etch suffers more damage compared to gate stacks on (100)-oriented In0.53Ga0.47As. To minimise the etching damage, cyclic TMA/plasma gas pretreatment prior to ALD is introduced on both (100)- and (110)-oriented surfaces. The interface trap density of gate stacks on (110)-oriented In0.53Ga0.47As with TMA/H2 gas pre-treatment improves from 6 × 1011 cm-2eV-1 to 2.8 × 1011 cm-2eV-1 close to the conduction band edge.

Based on this in-situ gate stack process, a gate stack with reduced capacitor equivalent thickness (CET) on both (100) and (110) oriented surfaces are achieved by using a TiN layer deposited in-situ by ALD before ex-situ gate metal deposition. The lowest CET was around 1.09 nm for a HfO2/TiN stack deposited on (100)-oriented In0.53Ga0.47As.

This optimised gate stack was included in an InGaAs-based tunnel-FET process flow using p-n, p-i-n, and p-n-i-n heterostructures. Comparing with p-n Tunnel-FETs, the pi-n structure provides better electrical characteristics for In0.53Ga0.47As with a subthreshold swing (SS) of 120 mV/dec at the condition of VDS = 0.05V. The peak transconductance peak of the p-i-n Tunnel-FET at the condition of VDS = 0.3V is around 6 uS/um. Next, an inserted n-pocket p-n-i-n Tunnel-FET was studied. In addition to providing comparable on current with the p-i-n Tunnel-FET of 1.1 uA/um at the bias condition of VDS = 300mV, the subthreshold swing of the p-n-i-n devices improves by 46% due to the lower leakage floor from the n-pocket layer incorporation. Most importantly, the non-planar configuration of the p-n-i-n Tunnel-FET improves both the SS and on-current to 152 mV/dec at the bias condition of VDS = 300mV and 1.3 uA/um at the bias condition of VDS = 500mV and VGS = 900mV, respectively. Above these aspects and benchmark, all this data implies that a non-planar p-n-i-n InGaAs TunnelFET is a promising candidate for future generations of low power applications.

• Item Type: Thesis (PhD)
• Qualification Level: Doctoral
• Keywords: InGaAs, (110) orientation, MOSCAP, FGA, Tunnel-FET.
• Subjects: Q Science > QC Physics; T Technology > TK Electrical engineering. Electronics Nuclear engineering
• Colleges/Schools: College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
• Supervisor's Name: Thayne, Professor Iain
• Date of Award: 2018
• Depositing User: Yen-Chun Fu
• Unique ID: glathesis:2018-30588
• Copyright: Copyright of this thesis is held by the author.
• Date Deposited: 31 Jul 2018 09:24
• Last Modified: 13 Jun 2019 14:42
• URI: https://theses.gla.ac.uk/id/eprint/30588

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