Scaling and variability in ultra thin body silicon on insulator (UTB SOI) MOSFETs

Mohd Zain, Anis Suhaila (2013) Scaling and variability in ultra thin body silicon on insulator (UTB SOI) MOSFETs. PhD thesis, University of Glasgow.

Abstract

The main objective of this thesis is to perform a comprehensive simulation study of the
statistical variability in well scaled fully depleted ultra thin body silicon on insulator
(FD-UTB SOI) at nanometer regime. It describes the design procedure for template FDUTB
SOI transistor scaling and the impacts of statistical variability and reliability the
scaled template transistor.
The starting point of this study is a systematic simulation analysis based on a welldesigned
32nm thin body SOI template transistor provided by the FP7 project
PULLNANO. The 32nm template transistor is consistent with the International
Technology Roadmap for Semiconductor (ITRS) 2009 specifications. The wellestablished
3D ‘atomistic’ simulator GARAND has been employed in the designing of
the scaled transistors and to carry out the statistical variability simulations. Following
the foundation work in characterizing and optimizing the template 32 nm gate length
transistor, the scaling proceeds down to 22 nm, 16 nm and 11 nm gate lengths using
typically 0.7 scaling factor in respect of the horizontal and vertical transistor
dimensions. The device design process is targeted for low power applications with a
careful consideration of the impacts of the design parameters choice including buried
oxide thickness (TBOX), source/drain doping abruptness (σ) and spacer length (Lspa). In
order to determine the values of TBOX, σ, and Lspa, it is important to analyze simulation
results, carefully assessing the impact on manufacturability and to consider the
corresponding trade-off between short channel effects and on-current performance.
Considering the above factors, TBOX = 10nm, σ = 2nm/dec and Lspa = 7nm have been
adopted as optimum values respectively.
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The statistical variability of the transistor characteristics due to intrinsic parameter
fluctuation (IPF) in well-scaled FD-UTB SOI devices is systematically studied for the
first time. The impact of random dopant fluctuation (RDF), line edge roughness (LER)
and metal gate granularity (MGG) on threshold voltage (Vth), on-current (Ion) and drain
induced barrier lowering (DIBL) are analysed. Each principal sources of variability is
treated individually and in combination with other variability sources in the simulation
of large ensembles of microscopically different devices. The introduction of highk/
metal gate stack has improved the electrostatic integrity and enhanced the overall
device performance. However, in the case of fully depleted channel transistors, MGG
has become a dominant variability factor for all critical electrical parameters at gate first
technology. For instance, σVth due to MGG increased to 41.9 mV at 11nm gate length
compared to 26.0 mV at 22nm gate length. Similar trend has also been observed in σIon,
increasing from 0.065 up to 0.174 mA/μm when the gate length is reduced from 22 nm
down to 11 nm. Both RDF and LER have significant role in the intrinsic parameter
fluctuations and therefore, none of these sources should be overlooked in the
simulations.
Finally, the impact of different variability sources in combination with positive bias
temperature instability (PBTI) degradation on Vth, Ion and DIBL of the scaled
nMOSFETs is investigated. Our study indicates that BTI induced charge trapping is a
crucial reliability problem for the FD-UTB SOI transistors operation. Its impact not
only introduces a significant degradation of transistor performance, but also accelerates
the statistical variability. For example, the effect of a late degradation stage (at trap
density of 1e12/cm2) in the presence of RDF, LER and MGG results in σVth increase to
36.9 mV, 45.0 mV and 58.3 mV for 22 nm, 16 nm and 11 nm respectively from the
original 29.0 mV, 37.9 mV and 50.4 mV values in the fresh transistors.

• Item Type: Thesis (PhD)
• Qualification Level: Doctoral
• Subjects: T Technology > TA Engineering (General). Civil engineering (General)
• Colleges/Schools: College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
• Supervisor's Name: Asenov, Prof. Asen
• Date of Award: 2013
• Depositing User: Mrs Anis Suhaila Mohd Zain
• Unique ID: glathesis:2013-4281
• Copyright: Copyright of this thesis is held by the author.
• Date Deposited: 24 May 2013 14:11
• Last Modified: 24 May 2013 14:11
• URI: https://theses.gla.ac.uk/id/eprint/4281