InAlN/AlGaN/GaN high electron mobility transistors on Si substrates

Floros, Konstantinos (2019) InAlN/AlGaN/GaN high electron mobility transistors on Si substrates. PhD thesis, University of Glasgow.

Abstract

Nowadays, improvements in the energy efficiency of silicon (Si) power electronics are becoming less substantial, as Si is approaching its theoretically predicted limits. Gallium nitride (GaN) transistors are candidates for the next era of power electronics due to a unique set of properties that enable increased power per unit area compared to Si. The industry transition to GaN is also cost effective, as GaN can be run on existing Si process lines using GaN-on-Si heteroepitaxy.

This work investigates a “dual barrier” InAlN/AlGaN/GaN-on-silicon high electron mobility transistor (HEMT) technology with respect to its suitability for power electronic transistor development and reports routes to the realisation of enhancement mode and depletion mode transistors through its use. The material structures were grown to satisfy high conductivity in the access regions and compatibility with several gate process modules which can allow for normally-off operation.

Experimental testing of material and transistor properties was performed through parametric studies aiding process optimisation. Carrier transport characteristics were obtained and material sheet resistances as low as 258 Ω/sq were determined. Mesa etch isolation over a 3 μm x 100 μm gap and HEMT off-state leakage were in the order of 100 nΑ/mm for a 200 V sweep. Access to the 2DEG was obtained through thermally optimised ohmic contacts of as low as 0.44 Ω mm contact resistance.

Depletion mode (normally-on) devices fabricated on 8 nm ΙnAlN/3 nm AlGaN/GaN-on-Si wafers exhibited maximum drain-source currents of 1A/mm, transconductance ~203 mS/mm and nearly ideal subthreshold swing ~65.6 mV/dec at 300 K. A two order of magnitude reduction from in gate leakage currents was achieved via the incorporation of Pt-based gate contacts compared to Ni gate stacks. For gate-source voltage VGS = -4 V, gate leakage current was 0.6 mA/mm for Ni/Au gate contacts, whilst this metric was 3.4 * 10-4 mA/mm for Pt/Au contacts. For gate-source voltage VGS = 3 V, the Ni/Au based gate contacts exhibited 1 mA/mm gate leakage current, compared to 3.7 * 10-6 mA/mm gate leakage current when Pt/Au gate contacts were used. Passivation via ICP SiNx was found to greatly enhance the channel conductivity, a property that was reversed via the use of SiNx bilayers of different stress. The performance of InAlN/AlGaN/GaN HEMT was compared to AlGaN/GaN devices for reference.

Gate process engineering techniques were developed, as means for shifting the threshold voltage of InAlN/AlGaN/GaN devices. Enhancement mode (normally-off) devices were demonstrated, exhibiting threshold voltage of +4.5 V via a selective wet etch process, based on ethylenediamine and free from plasma induced damage. Achieving a positive threshold voltage is critical for fail-safe operation. Compared to depletion mode devices fabricated on the same wafers, enhancement mode InAlN/AlGaN/GaN devices incorporating a SiCl4 based gate recess etch process showed a ~50% increase in extrinsic transconductance which is attributed to the decrease of the separation of the channel from the gate contact and the subsequent increased gate control.

As mentioned above, normally-off operation of GaN based transistors is important for power transistors and as such there is merit in performing ohmic contact optimisation work directly on enhancement mode materials. Evaluation of ohmic contacts was performed using gated TLM structures. The impact of these structures was analysed as it was found to significantly influence the extracted contact and sheet resistance characteristics due to the gate potential.

• Item Type: Thesis (PhD)
• Qualification Level: Doctoral
• Keywords: GaN, InAlN, HEMT, FET, AlGaN, dual barrier, double heterostructure, enhancement mode, normally off, depletion mode, normally on, threshold voltage, etching, fabrication, process, transistor, device, contacts, gated TLM, GaN on Si.
• Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
• Colleges/Schools: College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
• Funder's Name: Engineering and Physical Sciences Research Council (EPSRC)
• Supervisor's Name: Thayne, Professor Iain G.
• Date of Award: 2019
• Embargo Date: 1 March 2024
• Depositing User: Konstantinos Floros
• Unique ID: glathesis:2019-80299
• Copyright: Copyright of this thesis is held by the author.
• Date Deposited: 27 Apr 2020 14:01
• Last Modified: 30 Mar 2023 11:01
• URI: https://theses.gla.ac.uk/id/eprint/80299

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