Heterointerface control in III-V nanowires monolithically integrated on silicon

Brugnolotto, Enrico (2024) Heterointerface control in III-V nanowires monolithically integrated on silicon. PhD thesis, University of Glasgow.

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Integration of photonic integrated circuits (PICs) serving as interconnects on the silicon electronic platform is gaining momentum as computational requirements increase. Due to material compatibility, silicon-based photonic components remain the main choice for industrial integration. However, research focused on integrating III-V semiconductor-based photonic components has made great progress in tackling the problem of lattice mismatch, which has hindered the use of this material on silicon platforms so far.
A promising monolithic method for the integration of III-V components in CMOS wafers is template assisted selective epitaxy (TASE), which employs a silicon oxide (SiO2) template to guide the metal-organic chemical vapor deposition (MOCVD) of III-V devices from a silicon seed defined in the device layer of a silicon on insulator (SOI) wafer. TASE enables high defect control but is still affected by a multifaceted growth front, which limits its compositional control and efficient integration of quantum confinement structures.
This work focuses on the monolithic growth of III-V nanowires from silicon, and, in particular, on the control of the morphology of the growth front and the sharpness of heterointerfaces as enablers for the creation of superlattices embedded in the nanowires. Stabilisation of a growth front consisting of a single {111}B facet was achieved on two SOI wafers with (001) and (110) device layer crystallographic orientations by exploiting the growth of InP with high precursor V / III ratios. With an overall growth yield of 92.55 % calculated on a sample of 15840 growth sites on two (110) chips, the method has proven to be very reliable even under laboratory conditions.
This method enabled the fabrication of InGaAs and InAs quantum wells in a InP matrix. Compositionally sharp heterointerfaces and perfect alignment of concentration profiles of the V and III group elements in the sub-10 nm layers were achieved by employing hold steps in the MOCVD recipe. The growth regime was estimated to be "layer-by-layer", with a very early stabilisation of a single {111}B facet as the growth front, as single crystals resulting from the merging of crystals grown from three nucleation sites were observed with the methodology used in this study. These merged crystals had a crystalline quality fully comparable to that of crystals grown from a single seed.
The growth rate homogeneity and highly predictable heterointerface positioning achieved in this work are expected to aid in the monolithic integration of photonic devices on the wafer scale. The integration of quantum well structures demonstrated in this thesis into the intrinsic region of p - i - n photodiodes and their in-depth electrooptical characterisation are the natural next step in proving an improvement in the performance of TASE-based photodetectors. Such an improvement, in conjunction with recent progress on TASE based modulators and microdisk lasers, will enable a fully TASE-fabricated PIC.

Item Type: Thesis (PhD)
Qualification Level: Doctoral
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Colleges/Schools: College of Science and Engineering > School of Engineering
Funder's Name: European Commission (EC)
Supervisor's Name: Georgiev, Professor Vihar
Date of Award: 2024
Depositing User: Theses Team
Unique ID: glathesis:2024-84374
Copyright: Copyright of this thesis is held by the author.
Date Deposited: 20 Jun 2024 13:29
Last Modified: 03 Jul 2024 08:19
Thesis DOI: 10.5525/gla.thesis.84374
URI: https://theses.gla.ac.uk/id/eprint/84374
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