Implementing video compression algorithms on reconfigurable devices

Stewart, Graeme Robert (2010) Implementing video compression algorithms on reconfigurable devices. EngD thesis, University of Glasgow.

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The increasing density offered by Field Programmable Gate Arrays(FPGA), coupled with their short design cycle, has made them a popular choice for implementing a wide range of algorithms and complete systems. In this thesis the implementation of video compression algorithms on FPGAs is studied. Two areas are specifically focused on; the integration of a video encoder into a complete
system and the power consumption of FPGA based video encoders.

Two FPGA based video compression systems are described, one which targets surveillance applications and one which targets video conferencing applications. The FPGA video surveillance system makes use of a novel memory format to
improve the efficiency with which input video sequences can be loaded over the system bus.

The power consumption of a FPGA video encoder is analyzed. The results indicating that the motion estimation encoder stage requires the most power consumption. An algorithm, which reuses the intra prediction results generated during the encoding process, is then proposed to reduce the power consumed on an FPGA video encoder’s external memory bus. Finally, the power reduction algorithm is implemented within an FPGA video encoder. Results are given showing that, in addition to reducing power on the external memory bus, the algorithm also reduces power in the motion estimation stage of a FPGA based video encoder.

Item Type: Thesis (EngD)
Qualification Level: Doctoral
Subjects: T Technology > T Technology (General)
Colleges/Schools: College of Science and Engineering > School of Engineering
Supervisor's Name: Renshaw, Mr. David and Hannah, Mr. John
Date of Award: 2010
Depositing User: Mr Graeme Stewart
Unique ID: glathesis:2010-1267
Copyright: Copyright of this thesis is held by the author.
Date Deposited: 22 Apr 2010
Last Modified: 10 Dec 2012 13:36

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