Analog integrated circuit design empowered by artificial intelligence techniques: from building blocks to small systems

Hao, Yijia (2025) Analog integrated circuit design empowered by artificial intelligence techniques: from building blocks to small systems. PhD thesis, University of Glasgow.

Abstract

Analog integrated circuit (IC) design remains a major bottleneck in modern electronic systems due to its reliance on expertise-driven iteration and the growing complexity of performance, robustness, and variability requirements. This dissertation aims to advance artificial intelligence (AI)-driven analog IC design methodologies across three hierarchical levels: building blocks, subsystems, and systems.

At the block level, a design–insight–aware comparison is conducted across representative circuits including a StrongARM comparator, two Miller-compensated operational amplifiers, and an LC voltage-controlled oscillator (VCO) to benchmark AI-assisted optimization against conventional systematic flows. Post-layout and silicon measurement results demonstrate that AI-assisted frameworks can achieve superior performance and robustness while preserving design intent.

At the subsystem level, the first AI-driven co-design flow for VCO–LDO integration is introduced. By simultaneously optimizing both blocks under supply–noise coupling and frequency–pushing effects, the method improves phase noise, figure of merit (FoM), and runtime efficiency compared to sequential design, demonstrating the value of cross-block optimization.

At the system level, a global–local optimization framework with multi-fidelity simulation is proposed for asynchronous successive-approximation register analog-to-digital converter. This methodology cascades surrogate model-based global exploration with parallel pattern search refinement, achieving competitive FoM across 12 design cases (7–12 bit, up to 250 MHz) with significantly reduced runtime and minimal manual effort.

Together, these contributions establish a practical pathway for AI-driven analog IC design automation. By combining black-box optimization, learning-based acceleration, and designer in-the-loop validation, this work demonstrates measurable gains in design quality, robustness, and time efficiency, offering a foundation for future system-level EDA tools.

• Item Type: Thesis (PhD)
• Qualification Level: Doctoral
• Subjects: T Technology > T Technology (General)
• Colleges/Schools: College of Science and Engineering > School of Engineering
• Supervisor's Name: Liu, Professor Bo and Cochran, Professor Sandy
• Date of Award: 2025
• Depositing User: Theses Team
• Unique ID: glathesis:2025-85613
• Copyright: Copyright of this thesis is held by the author.
• Date Deposited: 24 Nov 2025 13:39
• Last Modified: 24 Nov 2025 14:23
• Thesis DOI: 10.5525/gla.thesis.85613
• URI: https://theses.gla.ac.uk/id/eprint/85613

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