Accurate CMOS compact model and the corresponding circuit simulation in the presence of statistical variability and ageing

Ding, Jie (2015) Accurate CMOS compact model and the corresponding circuit simulation in the presence of statistical variability and ageing. PhD thesis, University of Glasgow.

Abstract

As CMOS scales down to sub-50 nm, it faces critical dimensions of charge and matter granularities, leading to the drastic increase of device parameter dispersion, named statistical variability, which is one of the main contemporary challenges for further downscaling and makes each device atomistically different leading to broad dispersion of their electrical characteristics. In addition, device reliability concerns gain inertia; among them Bias Temperature Instability (BTI) shortens device lifetime by trapping charges in defect states of the insulator or at the interface. The interplay between statistical variability and BTI results in more variations on device performance and thus greatly affect circuit performance. In turn design methodologies must evolve towards variability and reliability aware design. To do so statistical compact models including both the effects of statistical variability and BTI-induced ageing are required for the large-scale statistical circuit simulation of variability and reliability.

In this study, the application of accurate compact models, that describe performance variation in the presence of both statistical variability and reliability at arbitrary BTI-induced ageing levels, to SRAM circuit simulation is described. Both SRAM cell stability and write performance are evaluated and it is seen that, due to the accurate description of device performance distributions provided by the compact models and the sensitivity of these SRAM performance metrics on device performance, the approach presented here is better suited to high-sigma statistical circuit analysis than conventional approaches based upon assumed Gaussian distributions. The approach is demonstrated using a 25 nm gate length bulk MOSFET whose performance variation is obtained from statistical TCAD simulation using the GSS simulator GARAND. The simulated performance data is then used directly as the target for BSIM4 compact model extraction that ensures device figures of merit are well resolved for each device in a statistical ensemble. The distribution of compact model parameters is then generalised into an algebraic form using Generalized Lambda Distribution (GLD) methods, so that a sufficiently large number of compact models can later be generated and interpolated at arbitrary ageing levels. Finally compact models generated in this way are used to evaluate SRAM write performance and stability under the influence of statistical variability and BTI-induced ageing.

• Item Type: Thesis (PhD)
• Qualification Level: Doctoral
• Additional Information: Funded from James Watt Scholarship and European project MORDRED.
• Keywords: CMOS, Compact Model, SRAM
• Subjects: T Technology > T Technology (General)
• Colleges/Schools: College of Science and Engineering > School of Engineering > Electronics and Nanoscale Engineering
• Supervisor's Name: Asenov, Professor Asen
• Date of Award: 2015
• Depositing User: Miss Jie Ding
• Unique ID: glathesis:2015-6864
• Copyright: Copyright of this thesis is held by the author.
• Date Deposited: 09 Nov 2015 13:23
• Last Modified: 07 Dec 2015 13:53
• URI: https://theses.gla.ac.uk/id/eprint/6864